A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack composed of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.
Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of carriers in the channel. Thus, the higher the mobility of the carriers in the channel, the more current can flow and the faster a circuit can perform when using high mobility MOS transistors. One way to increase the mobility of the carriers in the channel of a MOS transistor is to produce a mechanical stress in the channel.
A compressive strained channel has significant hole mobility enhancement over conventional devices. A tensile strained channel, such as a thin silicon channel layer grown on relaxed silicon-germanium, achieves significant electron mobility enhancement. The most common method of introducing tensile strain in a silicon channel region is to epitaxially grow the silicon channel layer on a relaxed silicon-germanium (SiGe) layer or substrate. The ability to form a relaxed SiGe layer is important in obtaining an overlying, epitaxially grown, silicon layer under biaxial tensile strain; however the attainment of the relaxed SiGe layer can be costly and difficult to achieve.
Another prior art method of obtaining a compressive strain in the channel is to epitaxially grow a SiGe layer over the entire active area. However, processes using selective epitaxial deposition for the engineering of elevated source/drain regions often result in overgrowth of the SiGe layer, typically on the order of 300 to 400 Angstroms. Such overgrowth on free surfaces results in faceting of edges due to minimization of interfacial energy causing strain relaxation along corners and potential strain in the channel. Similar to free surfaces, faceting also occurs in the presence of an oxide. Thus, SiGe along the edge of a shallow trench isolation (STI) is faceted, resulting in decreased strain in narrow devices.
It would be advantageous to have a semiconductor device and method that effectively and reliably provides strain to the device without the problems associated with faceting.